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d a t a sh eet preliminary speci?cation supersedes data of september 1992 file under integrated circuits, ic03 november 1994 integrated circuits philips semiconductors UMA1005t dual low-power frequency synthesizer
november 1994 2 philips semiconductors preliminary speci?cation dual low-power frequency synthesizer UMA1005t features fast locking by fractional-n divider auxiliary synthesizer digital phase comparator with proportional and integral charge pump output high-speed serial input low-power consumption programmable charge pump currents supply voltage range 2.9 to 5.5 v. applications mobile telephony portable battery-powered radio equipment. general description the UMA1005t is a low-power, high-performance dual frequency synthesizer fabricated in cmos technology. fractional-n division with selectable modulo 5 or 8 is implemented in the main synthesizer. the detectors and charge pumps are designated to achieve 10 to 5000 khz channel spacing using fractional-n decreases the channel spacing by a factor 5 or 8. together with an external standard 2, 3 or 4 ratio prescaler the main synthesizer can operate in the ghz frequency range. channel selection and programming is realized by a high-speed 3-wire serial interface. ordering information type number package name description version UMA1005t ssop20 plastic shrink small outline package; 20 leads; body width 4.4 mm sot266-1
november 1994 3 philips semiconductors preliminary speci?cation dual low-power frequency synthesizer UMA1005t block diagram / 1 page = 296 mm (datasheet) 27 mm mea668 - 1 prescaler feedback normal output charge pump speed-up output charge pump integral output charge pump auxiliary output charge pump cn 8 cl 2 ck 4 main reference select sm 2 main phase detector em 2 2 2 2 auxiliary reference select sa 2 auxiliary phase detector ea 2 nf 3 fmod fractional accumulator frd nm4 4 nm2 nm3 8 nm1 12 pr 2 main dividers em 2 3 6 5 4 em + ea 7 ea 8 reference divider nr 12 pa na 12 auxiliary divider 41 17 10 9 11 13 18 19 16 15 fb1 fb2 rf rn php phi ra pha lock 20 12 14 1 v ddd v dda v ss v ssa ina inr inm2 inm1 strobe clock data UMA1005t serial input + program latches fig.1 block diagram.
november 1994 4 philips semiconductors preliminary speci?cation dual low-power frequency synthesizer UMA1005t pinning symbol pin description v ddd 1 digital supply voltage inm1 2 main divider positive input; rising edge active inm2 3 main divider negative input; falling edge active data 4 serial data input line clock 5 serial clock input line strobe 6 serial strobe input line inr 7 reference divider input line; rising edge active ina 8 auxiliary divider input line; rising edge active ra 9 auxiliary current setting; resistor to v ss pha 10 auxiliary phase detector output phi 11 integral phase detector output v ssa 12 analog ground; internally connected to v ss php 13 proportional phase detector output v dda 14 analog supply voltage rn 15 main current setting input; resistor to v ss rf 16 fractional compensation current setting input; resistor to v ss lock 17 lock detector output fb1 18 feedback output 1 for prescaler modulus control fb2 19 feedback output 2 for prescaler modulus control v ss 20 common ground connection fig.2 pin configuration. 1/2 page (datasheet) 22 mm 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 UMA1005t inm1 inm2 data clock strobe inr ina ra pha fb2 fb1 lock rn php phi v dda v ssa mea667 rf v ddd v ss
november 1994 5 philips semiconductors preliminary speci?cation dual low-power frequency synthesizer UMA1005t functional description serial programming input the serial input is a 3-wire input (clock, strobe and data) to program all counter ratios, dacs, selection and enable bits. the programming data is structured into 24 or 32-bit words. each word includes 1 or 4 address bits. figure 3 shows the timing diagram of the serial input. when the strobe = low, the clock driver is enabled and on the positive edges of the clock the signal on the data input is clocked into a shift register. when the strobe = high, the clock is disabled and the data in the shift register remains stable. depending on the 1 or 4 address bits the data is latched into different working registers or temporary registers. in order to fully program the synthesizer, 4 words must be sent: 1. d word. 2. c word. 3. b word. 4. a word. figure 4 shows the format and the contents of each word. the e word is for testing purposes only. the e (test) word is reset when programming the d word. the data for nm4, cn and pr is stored by the b word temporary registers. when the a word is loaded, the data of these temporary registers is loaded together with the a word into the work registers which avoids false temporary main divider input. cn is only loaded from the temporary registers when a short 24-bit a0 word is used. cn will be directly loaded by programming a long 32-bit a1 word. the flag long in the d word determines whether a0 (long = 0) or a1 (long = 1) format is applicable. the a word contains new data for the main divider. the a word is loaded only when a main divider synchronization signal is also active, to avoid phase jumps when reprogramming the main divider. the synchronization signal is generated by the main divider. it disables the loading of the a word each main divider cycle during maximum 300 main divider input cycles. to make sure that the a word will be correctly loaded the strobe signal must be high for at least 300 main divider input cycles. programming the a word also means that the main charge pumps on outputs php and phi are set into the speed-up mode as long as the strobe remains high. fig.3 serial input timing sequence. handbook, full pagewidth mbe121 data valid data change t suda t hda data clock t hc t lc v h v l v h v l d0 d1 d30 d31 v h v l t hst t sust clock disabled store data clock enabled shift in data strobe
november 1994 6 philips semiconductors preliminary speci?cation dual low-power frequency synthesizer UMA1005t fig.4 serial input word format. a ndbook, full pagewidth mbe122 nm3 nm2 nm2 cn 0 nf nm1 word d31 msb a1 lsb nm3 nm2 nm2 0 nf nm1 d23 d0 d0 a0 pr = ?1 pr ?1 b 1 nm4 cn c 000 ck cl pr 1 nr d 010 sm sa f 1na 0 0 1 pa 000 000 em ea m o d l o n g 1 e 111 d0 d23 test bits address bits
november 1994 7 philips semiconductors preliminary speci?cation dual low-power frequency synthesizer UMA1005t table 1 description of symbols used in fig.4 notes 1. x = dont care. 2. not including reset cycles and fractional-n effects. symbol bits (1) function nm1 12 number of main divider cycles when prescaler is programmed in ratio r1 (fb1 = 1; fb2 = 0); note 2 nm2 8 if pr = 01 number of main divider cycles when prescaler is programmed in ratio r2 (fb1 = 0; fb2 = 0); note 2 4 if pr 1 01 nm3 4 if pr = 1x number of main divider cycles when prescaler is programmed in ratio r3 (fb1 = 0; fb2 = 1); note 2 nm4 4 if pr = 11 or 00 number of main divider cycles when prescaler is programmed in ratio r4 (fb1 = 1; fb2 = 1); note 2 pr 2 prescaler type in use: pr = 01; modulus 2 prescaler pr = 10; modulus 3 prescaler pr = 11; modulus 4 prescaler pr = 00; modulus 4 prescaler (inhibit ratio 3) nf 3 fractional-n increment fmod 1 fraction-n modulus selection ?ag: 1 = modulo 8 0 = modulo 5 long 1 a word format selection ?ag: 0 = 24-bit a0 format 1 = 32-bit a1 format cn 8 binary current setting factor for main charge pumps cl 2 binary acceleration factor for proportional charge pump current ck 4 binary acceleration factor for integral charge pump current em 1 main divider enable ?ag ea 1 auxiliary divider enable ?ag sm 2 reference select for main phase detector sa 2 reference select for auxiliary phase detector nr 9 reference divider ratio na 9 auxiliary divider ratio pa 1 auxiliary prescaler mode: pa = 0; divide-by-4 pa = 1; divide-by-1 auxiliary variable divider the input signal on ina is amplified to a logic level by a single ended input buffer, which accepts low level ac coupled input signals. this input stage is enabled if the serial control bit ea = 1. disabling means that all currents in the input stage are switched off. a fixed divide by 4 is enabled if pa = 0. this divider has been optimized to accept a high-frequency (90 mhz at a supply voltage range of 4.75 to 5.5 v) input signal. if pa = 1 this divider is disabled and the input signal is fed directly to the second
november 1994 8 philips semiconductors preliminary speci?cation dual low-power frequency synthesizer UMA1005t stage, which is a 9-bit programmable divider with standard input frequency (30 mhz). the division ratio can be expressed as: if pa = 0; n = 4 na. if pa = 1; n = na; with na = 4 to 511. reference variable divider (fig.5) the input signal on inr is amplified to a logic level by a single ended input buffer, which accepts low level ac coupled input signals. this input stage is enabled by the or function of the serial input bits ea and em. disabling means that all currents in the input stage are switched off. the reference divider consists of a programmable divider by nr (nr = 4 to 511) followed by a 3-bit binary counter. the 2-bit sm determines which of the 4 output pulses is selected as main phase detector input. the 2-bit sa determines the selection of the auxiliary phase detector signal. to obtain the best time spacing for the main and auxiliary reference signals, the opposite output will be used for the auxiliary phase detector, reducing the possibility of unwanted interactions. for this reason the programmable divider produces a symmetric output pulse for even ratios and a 1 input cycle asymmetric pulse for odd ratios. main variable divider the input signals on inm1 and inm2 are amplified to a logic level by a balanced input comparator giving a common mode rejection. this input stage is enabled when serial control bit em = 1. disabling means that all currents in the comparator are switched off. the main divider is built-up by a 12-bit counter plus a sign bit. depending on the serial input values of nm1, nm2, nm3, nm4 and the prescaler select pr, the counter will select a prescaler ratio during a number of input cycles in accordance with the information in table 2. fig.5 reference variable divider. b ook, full pagewidth mbe123 divide by nr reference input 2 22 main select sm = ?0 sm = ?1 sm = ?0 sm = ?1 main phase detector auxiliary select sa = ?1 sa = ?0 sa = ?1 sa = ?0 auxiliary phase detector
november 1994 9 philips semiconductors preliminary speci?cation dual low-power frequency synthesizer UMA1005t table 2 selection of prescaler ratio notes 1. x = dont care. 2. when the fractional accumulator overflows. the total division ratio from prescaler to the phase detector expressions are given in table 3. table 3 total division from prescaler to phase detector expressions note 1. when the fractional accumulator overflows. when the prescaler ratio is r2 = r1 + 1 the total division ratio n =n+1. table 4 modulus prescaler counter status fb1 fb2 prescaler ratio (1) ( - nm1 - 1) to 0 1 0 r1 ( - nm1 - 1) to - 11 0r1 (2) 1 to nm2 0 0 r2 0 to nm2 0 0 r2 (2) 0 to nm3 0 1 r3; if pr = 1x 0 to nm4 1 1 r4; if pr = 11 or 00 condition expression pr = 01 n = (nm1 + 2) r1 + nm2 r2 n = (nm1 + 1) r1 + (nm2 + 1) r2; note 1 pr = 10 n = (nm1 + 2) r1 + nm2 r2 + (nm3 + 1) r3 n = (nm1 + 1) r1 + (nm2 + 1) r2 + (nm3 + 1) r3; note 1 pr = 11 n = (nm1 + 2) r1 + nm2 r2 + (nm3 + 1) r3 + (nm4 + 1) r4 n = (nm1 + 1) r1 + (nm2 + 1) r2 + (nm3 + 1) r3 + (nm4 + 1) r4; note 1 pr = 00 n = (nm1 + 2) r1 + nm2 r2 + (nm4 + 1) r4 n = (nm1 + 1) r1 + (nm2 + 1) r2 + (nm4 + 1) r4; note 1 pr modulus prescaler bit capacity nm1 nm2 nm3 nm4 00 4 12 4 - 4 01 2 12 8 -- 10 3 12 4 4 - 11 4 12 4 4 4
november 1994 10 philips semiconductors preliminary speci?cation dual low-power frequency synthesizer UMA1005t the loading of the work registers nm1, nm2, nm3, nm4 and pr is synchronized with the state of the main counter, to avoid extra phase disturbance when switching over to another main divider ratio as is explained in section serial programming input. at the completion of a main divider cycle, a main divider output pulse is generated which will drive the main phase comparator. also the fractional accumulator is incremented with nf. the accumulator works modulo q. q is preset by the serial control bit fmod to 8 when fmod = 1. each time the accumulator overflows, the feedback to the prescaler will select one cycle using prescaler ratio r2 instead of r1. as shown above, this will increase the overall division ratio by 1 if r2 = r1 + 1. the mean division ratio over q main divider cycles will then be: programming a fraction means the prescaler with main divider will divide by n or n + 1. the output of the main divider will be modulated with a fractional phase ripple. this phase ripple is proportional to the contents of the fractional accumulator frd, which is used for fractional current compensation. phase detectors (fig.6) the auxiliary and main phase detectors are a 2 d-type flip-flop phase and frequency detector. the flip-flops are set by the negative edges of output signals of the dividers. the reset inputs are activated when both flip-flops have been set and when the reset enable signal is active (low). around zero phase error this has the effect of delaying the reset for 1 reference input cycle. this avoids non-linearity or dead band around zero phase error. the flip-flops drive on-chip charge pumps. a pull-up current from the charge pump indicates that the vco frequency shall be increased while a pull-down pulse indicates that the vco frequency shall be decreased. current settings the UMA1005t has 3 current setting pins ra, rn and rf. the active charge pump currents and the fractional compensation currents are linearly dependent on the current in the current setting pins. this current i r can be set by an external resistor to be connected between the current setting pin (pin 9) and v ss . the typical value for r (current setting resistor) can be calculated with the nq n nf q ------- - + = equation: the current can be set to zero by connecting the corresponding pin to v dda . auxiliary output charge pumps the auxiliary charge pumps on pin pha are driven by the auxiliary phase detector and the current value is determined by the external resistor (r ext ) at pin ra. the active charge pump current is typically: |i pha |=8 i ra . main output charge pumps and fractional compensation currents the main charge pumps on pins php and phi are driven by the main phase detector and the current value is determined by the current at pin rn and via a number of dacs which are driven by registers of the serial input. the fractional compensation current is determined by the current at pin rf, the contents of the fractional accumulator frd and a number of dacs driven by registers from the serial input. the timing for the fractional compensation is derived from the reference divider. the current is on during 1 input reference cycle before and 1 cycle after the output signal to the phase comparator. figure 7 shows the waveforms for a typical case. when the serial input a word is loaded, the output circuits are in the speed-up mode as long as the strobe is high, else the normal mode is active. n ormal mode in the normal mode the current output at php is: i php(n) =i pump10 +i comp10 . where: ; charge pump current. ; fractional compensation current. in normal mode the current at output phi is zero. r v dda 0.5 C () 237 i r C i r ------------------------------------------------------------ - = i pump10 cn i rn 29 ----------------------- - = i comp10 frd i rf 128 --------------------------- =
november 1994 11 philips semiconductors preliminary speci?cation dual low-power frequency synthesizer UMA1005t handbook, full pagewidth mbe124 inr l r x p n ph auxiliary and main divider r d c q r d c q ? x ? r l reference divider inr v ssa v dda p n p-type charge pump n-type charge pump ph fig.6 phase detector structure with timing.
november 1994 12 philips semiconductors preliminary speci?cation dual low-power frequency synthesizer UMA1005t s peed - up mode in speed-up mode the current in output php is: i php(s) =i php(n) +i pump11 +i comp11 . where: i pump11 =i pump10 2 (cl + 1) ; charge pump current. i comp11 =i comp10 2 (cl + 1) ; fractional compensation current. in speed-up mode the current in output phi is: i phi(s) =i pump21 +i comp21 . where: i pump21 =i pump11 ck; charge pump current. i comp21 =i comp11 ck; fractional compensation current. figure 7 shows that for a proper fractional compensation the area of the fractional compensation current pulse must be equal to the area of the charge pump ripple output. this means that the current setting on the inputs rn and rf must have following ratio: . where: q = fractional-n modulus. f vco =f i(max)1 n; input frequency of the prescaler. f i(max)1 = maximum input frequency of the main divider (pins inm1 and inm2). f i(max)2 = maximum input frequency of the reference divider (pin inr). lock detect the output lock is high when the auxiliary phase detector and the main phase detector indicate a lock condition. the lock condition is defined as a phase difference of less than 1 cycle on the reference input inr. the lock condition is also fulfilled when the relative counter is disabled (em = 0 or ea = 0 respectively) for the main or auxiliary counter respectively. i rn i rf -------- 29 q f vco 64 cn f imax () 2 ------------------------------------------------ =
november 1994 13 philips semiconductors preliminary speci?cation dual low-power frequency synthesizer UMA1005t handbook, full pagewidth mbe125 inr inm n n n 1n n 1 detector output contents accumulator 2 4 1 3 0 fractional compensation current pulse-width modulation ma m a t 1 t 2 pulse-level modulation outputs php and phi fig.7 waveforms for nf = 2 and fraction = 0.4.
november 1994 14 philips semiconductors preliminary speci?cation dual low-power frequency synthesizer UMA1005t limiting values in accordance with the absolute maximum rating system (iec 134). dc characteristics v ddd =v dda = 2.9 to 5.5 v; t amb = - 40 to +70 c; unless otherwise speci?ed. symbol parameter min. max. unit v ddd digital supply voltage - 0.5 6.5 v v dda analog supply voltage - 0.5 6.5 v v i voltage on any input - 0.5 v dd + 0.5 v i n dc current into any input or output - 10 +10 ma p tot total power dissipation - 25 mw t stg storage temperature - 65 +150 c t amb operating ambient temperature - 40 +70 c symbol parameter conditions min. typ. max. unit supply i ddd(stb) digital standby supply current em = ea = 0; inputs on v dd or 0 -- 5 m a i ddd operating digital supply current note 1 -- 5ma i dda(stb) analog standby supply current v ra =v dda ; v rf =v dda ; v rn =v dda -- 10 m a i dda operating analog supply current note 1 -- 0.6 ma digital inputs clk, data and strobe v ih high level input voltage 0.7v dd - v dd v v il low level input voltage 0 - 0.3v dd v digital outputs fb1, fb2 and lock v ol low level output voltage i o = 2 ma; note 2 -- 0.4 v v oh high level output voltage i o = - 2 ma; note 2 v dd - 0.4 -- v charge pump pha ? i pha ? output current i ra = - 62.5 m a; v pha = 1 2 v dd ; note 2 400 500 600 m a i ra = - 25 m a; v pha = 1 2 v dd 160 200 240 m a relative output current variation i ra = - 62.5 m a; notes 2 and 3 - 26 % d i pha m output current matching i ra = - 62.5 m a; v pha = 1 2 v dd ; notes 2 and 4 -- 50 m a d i pha i pha ---------------
november 1994 15 philips semiconductors preliminary speci?cation dual low-power frequency synthesizer UMA1005t charge pump php; normal mode (notes 5, 6 and 7) ; v rf =v dd ? i php(n) ? output current i rn = - 62.5 m a; v php = 1 2 v dd ; note 2 440 550 660 m a i rn = - 25 m a; v php = 1 2 v dd 175 220 265 m a d i php(n) relative output current variation i rn = - 62.5 m a; note 3 - 26 % d i php(n m) output current matching i rn = - 62.5 m a; v php = 1 2 v dd ; notes 2 and 4 -- 50 m a charge pump php; speed-up mode (notes 5, 6 and 8) ; v rf =v dd ? i php(s) ? output current i rn = - 62.5 m a; v php = 1 2 v dd ; note 2 2.20 2.75 3.30 ma i rn = - 25 m a; v php = 1 2 v dd 0.85 1.1 1.35 ma d i php(s) relative output current variation i rn = - 62.5 m a; notes 2 and 3 - 26 % d i php(s m) output current matching i rn = - 62.5 m a; v php = 1 2 v dd ; notes 2 and 4 -- 250 m a charge pump phi; speed-up mode (notes 5, 6 and 9) ; v rf =v dd ? i phi(s) ? output current i rn = - 62.5 m a; v phi = 1 2 v dd ; note 2 4.4 5.5 6.6 ma i rn = - 25 m a; v phi = 1 2 v dd 1.75 2.2 2.65 ma d i phi(s) relative output current variation i rn = - 62.5 m a; notes 2 and 3 - 28 % d i phi(s m) output current matching i rn = - 62.5 m a; v phi = 1 2 v dd ; notes 2 and 4 -- 500 m a fractional compensation php; normal mode (notes 5, 10 and 11) ; v rn =v dd ; v php = 1 2 v dd i php(f n) fractional compensation output current php as a function of frd i rf = - 62.5 m a; frd = 1 to 7; notes 2 and 12 - 675 - 500 - 325 na i rf = - 25 m a; frd=1to7; note 12 - 270 - 200 - 130 na fractional compensation php; speed-up mode (notes 5, 11 and 13) ; v rn =v dd ; v php = 1 2 v dd i php(f s) fractional compensation output current php as a function of frd i rn = - 62.5 m a; frd = 1 to 7; notes 2 and 12 - 3.35 - 2.50 - 1.65 m a i rn = - 25 m a; frd = 1 to 7; note 12 - 1.35 - 1.00 - 0.65 m a symbol parameter conditions min. typ. max. unit
november 1994 16 philips semiconductors preliminary speci?cation dual low-power frequency synthesizer UMA1005t notes 1. operational conditions: a) main and auxiliary divider enabled (em = ea = 1). b) na = 125. c) nr = 125. d) nm1 = 60. e) nm2 = 63. f) f i(max)1 =f i(max)2 = 15 mhz. g) f i(max)3 = 60 mhz. h) lock condition. i) normal mode; note 5 j) i rn =i rf =i ra =25 m a. k) cn = 255. l) pa = 0. 2. limited supply voltage range 4.5 to 5.5 v. 3. the relative output current variation is defined as: ; with v 1 = 0.7 v; v 2 =v dd - 0.8 v (see fig.8). 4. the output current matching is measured when both (positive and negative current) sections of the output charge pumps are on. 5. when a serial a word is programmed, the main charge pumps on php and phi are in the speed-up mode as long as strobe = high, otherwise the main charge pumps are in the normal mode. 6. monotonicity is guaranteed with cn = 0 to 255. 7. typical output current: ; specification condition: cn = 255. fractional compensation phi; speed-up mode (notes 5, 11 and 14) ; v rn =v dd ; v php = 1 2 v dd i phi(f) fractional compensation output current phi as a function of frd i rn = - 62.5 m a; frd = 1 to 7; notes 2 and 12 - 5.4 - 4.0 - 2.6 m a i rn = - 25 m a; frd = 1 to 7; note 12 - 2.15 - 1.60 - 1.05 m a charge pump leakage currents; charge pump not active i php(lo) output leakage current php normal mode; v php = 0.7 to v dda - 0.8 v note 5 - 10 750 na i phi(lo) output leakage current phi normal mode; v phi = 0.7 to v dda - 0.8 v note 5 - 10 100 na i pha(lo) output leakage current pha v pha = 0.7 to v dda - 0.8 v - 10 750 na symbol parameter conditions min. typ. max. unit d i o i o --------- 2 i 2 i 1 C i 2 i 1 + ----------------- - = i php(n) i rn C cn 29 -------- - =
november 1994 17 philips semiconductors preliminary speci?cation dual low-power frequency synthesizer UMA1005t 8. typical output current: ; specification conditions: a) cn = 255; cl = 1 or, b) cn = 75; cl = 3. 9. typical output current: ; specification conditions: a) cn = 160; cl = 3; ck = 1 or, b) cn = 160; cl = 2; ck = 2 or, c) cn = 160; cl = 1; ck = 4 or, d) cn = 160; cl = 0; ck = 8. 10. typical fractional compensation output current: ; specification condition: frd = 1 to 7. 11. the compensation current specified does not include the leakage current of this output. 12. frd is the value of the 3-bit fractional accumulator. 13. typical fractional compensation output current: ; specification conditions: frd=1to7; cl=1. 14. typical fractional compensation output current: ; specification conditions: a) frd=1to7; cl=1; ck=2 or, b) frd=1to7; cl=2; ck=1. i php(s) i rn C cn 2 cl 1 + () 1 + 29 ------------------------------- = i phi i rn C cn 2 cl 1 + () ck 29 -------- = i php(f n) i rf frd 128 ------------ - = i php(f s) i rf frd 2 cl 1 + () 1 + 128 ------------------------------- = i phi(f) i rf frd 2 cl 1 + () ck 128 --------- - =
november 1994 18 philips semiconductors preliminary speci?cation dual low-power frequency synthesizer UMA1005t ac characteristics v ddd =v dda = 2.9 to 5.5 v; t amb = - 40 to +70 c; unless otherwise speci?ed. symbol parameter conditions min. typ. max. unit main divider (inputs inm1 and inm2) f i(max)1 maximum input frequency 10 -- mhz note 1 30 -- mhz d v inm(p-p) differential input signal amplitude v inm1 - v inm2 (peak-to-peak value) 600 -- mv v cm common mode range for v inm1 and v inm2 1 - v dd - 1v t pd propagation delay time from i nm1 and i nm2 to fb1 and fb2 -- 60 ns note 1 - 18 30 ns msr mark-to-space ratio for differential input signals 35:65 - 65:35 z i(min) minimum input impedance resistive; note 2 5 -- k w capacitive; note 2 -- 5pf fig.8 relative output current variation. handbook, full pagewidth mbe126 i 2 i i 1 i 2 i 1 v 1 vv 2 o o
november 1994 19 philips semiconductors preliminary speci?cation dual low-power frequency synthesizer UMA1005t notes 1. limited supply voltage range 4.5 to 5.5 v. 2. periodically sampled; not 100% tested. reference divider (input inr) f i(max)2 maximum input frequency 15 -- mhz note 1 30 -- mhz v i(p-p) input signal amplitude ac coupled (peak-to-peak value) 300 -- mv z i(min) minimum input impedance resistive; note 2 5 -- k w capacitive; note 2 -- 5pf auxiliary divider (input ina) f i(max)3 maximum input frequency prescaler enabled; pa = 0 35 -- mhz prescaler enabled; pa = 0; note 1 90 -- mhz prescaler disabled; pa = 1 15 -- mhz prescaler disabled; pa = 1; note 1 30 -- mhz v i(p-p) input signal amplitude ac coupled (peak-to-peak value) 300 -- mv z i(min) minimum input impedance resistive; note 2 5 -- k w capacitive; note 2 -- 5pf serial interface (inputs data, clock and strobe); see fig.3 f clk clock frequency -- 10 mhz t hc clock high time 30 -- ns t lc clock low time 30 -- ns t suda data set-up time 30 -- ns t hda data hold time 30 -- ns t sust strobe set-up time 30 -- ns t hst strobe hold time 30 -- ns symbol parameter conditions min. typ. max. unit
november 1994 20 philips semiconductors preliminary speci?cation dual low-power frequency synthesizer UMA1005t package outline handbook, full pagewidth a mbc237 - 1 0.15 0 1.4 1.2 0.8 0.3 0.20 0.13 0.6 0.5 0 to 10 o 1.5 1.2 detail a s 6.75 6.40 0.1 s pin 1 index 0.6 0.2 (4x) 0.13 m (20x) 0.32 0.20 0.65 4.5 4.3 6.6 6.2 110 20 11 fig.9 plastic shrink small outline package; 20 leads; body width 4.4 mm (ssop20; sot266-1). dimensions in mm.
november 1994 21 philips semiconductors preliminary speci?cation dual low-power frequency synthesizer UMA1005t soldering plastic small-outline packages b ywave during placement and before soldering, the component must be fixed with a droplet of adhesive. after curing the adhesive, the component can be soldered. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. maximum permissible solder temperature is 260 c, and maximum duration of package immersion in solder bath is 10 s, if allowed to cool to less than 150 c within 6 s. typical dwell time is 4 s at 250 c. a modified wave soldering technique is recommended using two solder waves (dual-wave), in which a turbulent wave with high upward pressure is followed by a smooth laminar wave. using a mildly-activated flux eliminates the need for removal of corrosive residues in most applications. b y solder paste reflow reflow soldering requires the solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the substrate by screen printing, stencilling or pressure-syringe dispensing before device placement. several techniques exist for reflowing; for example, thermal conduction by heated belt, infrared, and vapour-phase reflow. dwell times vary between 50 and 300 s according to method. typical reflow temperatures range from 215 to 250 c. preheating is necessary to dry the paste and evaporate the binding agent. preheating duration: 45 min at 45 c. r epairing soldered joints ( by hand - held soldering iron or pulse - heated solder tool ) fix the component by first soldering two, diagonally opposite, end pins. apply the heating tool to the flat part of the pin only. contact time must be limited to 10 s at up to 300 c. when using proper tools, all other pins can be soldered in one operation within 2 to 5 s at between 270 and 320 c. (pulse-heated soldering is not recommended for so packages.) for pulse-heated solder tool (resistance) soldering of vso packages, solder is applied to the substrate by dipping or by an extra thick tin/lead plating before package placement. definitions life support applications these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips for any damages resulting from such improper use or sale. data sheet status objective speci?cation this data sheet contains target or goal speci?cations for product development. preliminary speci?cation this data sheet contains preliminary data; supplementary data may be published later. product speci?cation this data sheet contains ?nal product speci?cations. limiting values limiting values given are in accordance with the absolute maximum rating system (iec 134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the speci?cation is not implied. exposure to limiting values for extended periods may affect device reliability. application information where application information is given, it is advisory and does not form part of the speci?cation.
november 1994 22 philips semiconductors preliminary speci?cation dual low-power frequency synthesizer UMA1005t notes
november 1994 23 philips semiconductors preliminary speci?cation dual low-power frequency synthesizer UMA1005t notes
philips semiconductors philips semiconductors C a worldwide company argentina: ierod, av. juramento 1992 - 14.b, (1428) buenos aires, tel. (541)786 7633, fax. (541)786 9367 australia: 34 waterloo road, north ryde, nsw 2113, tel. (02)805 4455, fax. (02)805 4466 austria: triester str. 64, a-1101 wien, p.o. box 213, tel. (01)60 101-1236, fax. (01)60 101-1211 belgium: postbus 90050, 5600 pb eindhoven, the netherlands, tel. (31)40 783 749, fax. (31)40 788 399 brazil: rua do rocio 220 - 5 th floor, suite 51, cep: 04552-903-s?o paulo-sp, brazil. p.o. box 7383 (01064-970). tel. (011)821-2333, fax. (011)829-1849 canada: philips semiconductors/components: tel. (800) 234-7381, fax. (708) 296-8556 chile: av. santa maria 0760, santiago, tel. (02)773 816, fax. (02)777 6730 colombia: iprelenso ltda, carrera 21 no. 56-17, 77621 bogota, tel. (571)249 7624/(571)217 4609, fax. (571)217 4549 denmark: prags boulevard 80, pb 1919, dk-2300 copenhagen s, tel. (032)88 2636, fax. (031)57 1949 finland: sinikalliontie 3, fin-02630 espoo, tel. (9)0-50261, fax. (9)0-520971 france: 4 rue du port-aux-vins, bp317, 92156 suresnes cedex, tel. (01)4099 6161, fax. (01)4099 6427 germany: p.o. box 10 63 23, 20043 hamburg, tel. (040)3296-0, fax. (040)3296 213. greece: no. 15, 25th march street, gr 17778 tavros, tel. (01)4894 339/4894 911, fax. (01)4814 240 hong kong: philips hong kong ltd., 6/f philips ind. bldg., 24-28 kung yip st., kwai chung, n.t., tel. (852)424 5121, fax. (852)428 6729 india: philips india ltd, shivsagar estate, a block , dr. annie besant rd. worli, bombay 400 018 tel. (022)4938 541, fax. (022)4938 722 indonesia: philips house, jalan h.r. rasuna said kav. 3-4, p.o. box 4252, jakarta 12950, tel. (021)5201 122, fax. (021)5205 189 ireland: newstead, clonskeagh, dublin 14, tel. (01)640 000, fax. (01)640 200 italy: philips semiconductors s.r.l., piazza iv novembre 3, 20124 milano, tel. (0039)2 6752 2531, fax. (0039)2 6752 2557 japan: philips bldg 13-37, kohnan 2 -chome, minato-ku, tokyo 108, tel. (03)3740 5028, fax. (03)3740 0580 korea: (republic of) philips house, 260-199 itaewon-dong, yongsan-ku, seoul, tel. (02)794-5011, fax. (02)798-8022 malaysia: no. 76 jalan universiti, 46200 petaling jaya, selangor, tel. (03)750 5214, fax. (03)757 4880 mexico: 5900 gateway east, suite 200, el paso, tx 79905, tel. 9-5(800)234-7381, fax. (708)296-8556 netherlands: postbus 90050, 5600 pb eindhoven, bldg. vb tel. (040)783749, fax. (040)788399 new zealand: 2 wagener place, c.p.o. box 1041, auckland, tel. (09)849-4160, fax. (09)849-7811 norway: box 1, manglerud 0612, oslo, tel. (022)74 8000, fax. (022)74 8341 pakistan: philips electrical industries of pakistan ltd., exchange bldg. st-2/a, block 9, kda scheme 5, clifton, karachi 75600, tel. (021)587 4641-49, fax. (021)577035/5874546. philippines: philips semiconductors philippines inc, 106 valero st. salcedo village, p.o. box 2108 mcc, makati, metro manila, tel. (02)810 0161, fax. (02)817 3474 portugal: philips portuguesa, s.a., rua dr. antnio loureiro borges 5, arquiparque - miraflores, apartado 300, 2795 linda-a-velha, tel. (01)4163160/4163333, fax. (01)4163174/4163366. singapore: lorong 1, toa payoh, singapore 1231, tel. (65)350 2000, fax. (65)251 6500 south africa: s.a. philips pty ltd., 195-215 main road martindale, 2092 johannesburg, p.o. box 7430 johannesburg 2000, tel. (011)470-5911, fax. (011)470-5494. spain: balmes 22, 08007 barcelona, tel. (03)301 6312, fax. (03)301 42 43 sweden: kottbygatan 7, akalla. s-164 85 stockholm, tel. (0)8-632 2000, fax. (0)8-632 2745 switzerland: allmendstrasse 140, ch-8027 zrich, tel. (01)488 2211, fax. (01)481 77 30 taiwan: philips taiwan ltd., 23-30f, 66, chung hsiao west road, sec. 1. taipeh, taiwan roc, p.o. box 22978, taipei 100, tel. (02)388 7666, fax. (02)382 4382. thailand: philips electronics (thailand) ltd., 209/2 sanpavuth-bangna road prakanong, bangkok 10260, thailand, tel. (662)398-0141, fax. (662)398-3319. turkey: talatpasa cad. no. 5, 80640 gltepe/istanbul, tel. (0 212)279 2770, fax. (0212)269 3094 united kingdom: philips semiconductors ltd., 276 bath road, hayes, middlesex ub3 5bx, tel. (081)73050000, fax. (081)7548421 united states: 811 east arques avenue, sunnyvale, ca 94088-3409, tel. (800)234-7381, fax. (708)296-8556 uruguay: coronel mora 433, montevideo, tel. (02)70-4044, fax. (02)92 0601 for all other countries apply to: philips semiconductors, international marketing and sales, building be-p, p.o. box 218, 5600 md, eindhoven, the netherlands, telex 35000 phtcnl, fax. +31-40-724825 scd35 ? philips electronics n.v. 1994 all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. printed in the netherlands 413061/1500/02/pp24 date of release: november 1994 document order number: 9397 743 40011

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